1 ? fn6278.0 isl59117 triple channel video driver with lpf the isl59117 is a triple channe l reconstruction filter with a -3db roll-off frequency of 9mhz. operating from single supplies ranging from +2.5v to +3.6v and drawing only 3.9ma quiescent current, the isl59117 is ideally suited for low power, battery-operat ed applications. additionally, enable pins shut the part down in under 14ns. the isl59117 is designed to meet the needs for very low power and bandwidth required in battery-operated communication, instrumentation, and modern industrial applications such as video on demand, cable set-top boxes, mp3 players, and hdtv. the isl59117 is offered in a space-saving chipscale package guaranteed to a 0.57mm maximum height constraint and specified for operation from -40c to +85c temperature range. pinout isl59117 (wlcsp) top view features ? 3rd order 9mhz reconstruction filter ? 40v/s slew rate ? low supply current = 3.9ma ? power-down current less than 1a ? supplies from 2.5v to 3.6v ? rail-to-rail output ? csp package ? pb-free plus anneal available (rohs compliant) applications ? video amplifiers ? portable and handheld products ? communications devices ? video on demand ? cable set-top boxes ? satellite set-top boxes ? mp3 players ? hdtv ? personal video recorder block diagram a b 12 c 3 c in gnd c out cvbs in en cvbs out y in v dd y out x2 y in y out en x2 cvbs in cvbs out x2 c in c out + - 9mhz 9mhz 9mhz biasing & control 5a + - 5a 500mv 65mv 65mv 65mv + - + - + - ordering information part number (note) part marking tape and reel temp. range (c) package (pb-free) pkg. dwg. # ISL59117IIZ-T7 117z 7? -40 to +85 wlcsp w3x3.9a note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet september 21, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6278.0 september 21, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute m aximum ratings (t a = +25c) supply voltage from v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . 4.2v input voltage . . . . . . . . . . . . . . . . . . . . . . . v dd +0.3v to gnd -0.3v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c esd classification human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +125c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v dd = 3.3v, t a = +25c, r l = 150 ? to gnd, unless otherwise specified. parameter description conditions min typ max unit input characteristics v dd supply voltage range 2.5 3.6 v i dd quiescent supply current v in = 500mv, en = v dd , no load 3.9 6.5 ma i dd_off shutdown supply current en = 0v 0.1 0.5 a v y_clamp y input clamp voltage i y = -100a -30 -15 10 mv i y_down y input clamp discharge current v y = 0.5v 3 5 7 a i y_up y input clamp charge current v y = -0.1v -3.4 -2.5 ma r y y input resistance 0.5v < v y < 1v 10 m ? v cvbs_clamp cvbs input clamp voltage i y = -100a -30 -15 10 mv i cvbs_down cvbs input clamp discharge current v cvbs = 0.5v 357a i cvbs_up cvbs input clamp charge current v cvbs = -0.1v -3.4 -2.5 ma r cvbs cvbs input resistance 0.5v < v cvbs < 1v 10 m ? v c_clamp c input clamp voltage v y = 0.05v, i c = 0a 500 550 700 mv r c c input resistance v y = 0.05v, 0.25v < v c < 0.75v 2.0 2.6 3.0 k ? i c c input bias current v y = 0.3v 10 pa v y_sync y input sync detect voltage 100 150 200 mv v ols output level shift voltage v in = 0v, no load 60 140 200 mv a v voltage gain r l = 150 ? 1.95 1.99 2.04 v/v ? a v_cy c-y channel gain mismatch -1.75 0.5 1.75 % ? a v_cvbs c/y-cvbs channel gain mismatch -2.0 0.5 2.0 % psrr dc power supply rejection v dd = 2.5v to 3.6v 60 db v oh output voltage high swing v in = 2v, r l = 150 ? to gnd 2.85 3.2 v i sc output short-circuit current v in = 2v, to gnd through 10 ? 100 145 ma i enable enable input current 0v < v en < 3.3v -0.2 0 +0.2 a v il disable threshold 0.8 v v ih enable threshold 2.0 v r out shutdown output impedance en = 0v dc 5 7 8 k ? en = 0v, f = 4.5mhz 3.4 k ? isl59117
3 fn6278.0 september 21, 2006 connection diagram ac performance bw 0.1db 0.1db bandwidth r l = 150 ? , c l = 5pf 5 mhz bw 3db -3db bandwidth r l = 150 ? , c l = 5pf 9 mhz normalized stopband gain f = 27mhz -24.2 db dg differential gain ntsc and pal 0.10 % dp differential phase ntsc and pal 0.5 d/dt group delay variation f = 100khz, 5mhz 5.4 ns snr signal to noise ratio 100% white signal 65 db t on enable time v in = 500mv, v out to 1% 200 ns t off disable time v in = 500mv, v out to 1% 14 ns +sr positive slew rate 20% to 80%, v in = 1v step 30 40 60 v/s -sr negative slew rate 80% to 20%, v in = 1v step -30 -40 -60 v/s t f fall time 2.5v step , 80% - 20% 25 ns t r rise time 2.5v step , 20% - 80% 22 ns electrical specifications v dd = 3.3v, t a = +25c, r l = 150 ? to gnd, unless otherwise specified. (continued) parameter description conditions min typ max unit 75 cvbs out x2 y in y out x2 cvbs in cvbs out x2 c in c out + - 9mhz 9mhz 9mhz en biasing & control 5a + - 5a 500mv + - 65mv + - 65mv + - 65mv y (luminance) c (chrominance) cvbs (composite) 3.3v v dd 0.1f 0.1f 0.1f c or tie to 3.3v 0.1f 75 75 75 75 y out 75 c out s-video cable isl59117
4 fn6278.0 september 21, 2006 pin descriptions pin number pin name description a1 c in chrominance input a2 gnd ground a3 c out chrominance output b1 cvbs in composite video input b2 en enable b3 cvbs out composite video output c1 y in luminance input c2 v dd positive power supply c3 y out luminance output typical performance curves figure 1. gain vs frequency -0.1db figure 2. gain vs frequency -3db point figure 3. gain vs frequency for various c load figure 4. maximum output magnitude vs input magnitude 100k 1m 10m 5 4 3 2 1 -1 -2 -3 -5 normalized gain (db) frequency (hz) 100m v dd = +3.3v r l = 150 ? -0.1db bw @ 3.8mhz 0 -4 100k 1m 10m 5 0 -5 -10 -15 -20 -25 -30 -35 -40 frequency (hz) 40m v dd = +3.3v r l = 150 ? -3db bw @ 9mhz normalized gain (db) -30db bw @ 27mhz 100k 1m 10m 100m 5 4 3 2 1 0 -1 -2 -3 -4 -5 normalized gain (db) frequency (hz) v dd = +3.3v r l = 150 ? c l = 1000pf c l = 470pf c l = 10pf c l = 27pf 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v o u t ( v p - p ) v i n ( v p - p ) v dd = +3.3v r l = 150 ? f in = 100khz isl59117
5 fn6278.0 september 21, 2006 figure 5. phase vs frequency figure 6. psrr vs frequency figure 7. output impedance vs frequency figure 8. isolation vs frequency figure 9. maximum output vs load resistance figure 10. supply current vs supply voltage typical performance curves (continued) 100k 1m 10m 100m 270 180 90 0 -90 -180 -270 p h a s e ( ) frequency (hz) 10m v dd = +3.3v r l = 150 ? 100k 1m 10m 100m -20 -30 -40 -50 -60 -70 -80 -90 -100 p s r r ( d b ) frequency (hz) v dd = +3.3v 100k 1m 10m -40 -50 -60 -70 -80 -90 -100 -110 p s r r ( d b ) frequency (hz) 50m v dd = +3.3v c in to y out y in to c out v dd = +3.3v f in = 1mhz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 8 7 6 5 4 3 2 1 0 supply current (ma) supply voltage (v) no load no input isl59117
6 fn6278.0 september 21, 2006 figure 11. large signal step response f igure 12. small signal step response figure 13. enable time figure 14. disable time figure 15. harmonic distortion vs frequency fig ure 16. harmonic distortion vs output voltage typical performance curves (continued) -100 0 100 200 300 400 500 600 2.2 1.7 1.2 0.7 0.2 -0.3 time (ns) amplitude (v) v dd = +3.3v r l = 150 ? v out = 1v p-p t fall = 26.81ns t rise = 10.46ns -100 0 100 200 300 400 500 600 0.5 0.4 0.3 0.2 0.1 0 a m p l i t u d e ( v ) time (ns) v dd = +3.3v r l = 150 ? v out = 200mv p-p t fall = 27.92ns t rise = 27.85ns -100 -50 0 50 100 150 200 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 a m p l i t u d e ( v ) time (ns) v dd = +3.3v r l = 150 ? enable signal output signal -20 -10 0 10 20 30 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 a m p l i t u d e ( v ) time (ns) v dd = +3.3v r l = 150 ? disable signal output signal 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m -10 -20 -30 -40 -50 -60 -70 -80 h a r m o n i c d i s t o r t i o n ( d b ) frequency (hz) v dd = +3.3v r l = 150 ? v out = 2v p-p thd 3rd thd 2nd thd 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -10 -20 -30 -40 -50 -60 -70 -80 h a r m o n i c d i s t o r t i o n ( d b ) v out (v p-p ) v dd = +3.3v r l = 150 ? f in = 500khz thd 3rd thd 2nd thd isl59117
7 fn6278.0 september 21, 2006 figure 17. group delay vs frequency figure 18. -3db bandwidth vs input resistance figure 19. slew rate vs supply voltage figure 20. unweighted noise floor typical performance curves (continued) v dd = +3.3v r l = 150 ? 20 100 180 260 340 420 500 16 14 12 10 8 6 4 2 input resistance ( ? ) v dd = +3.3v r l = 150 ? - 3 d b b a n d w i d t h ( m h z ) 2.0 2.5 3.0 3.5 4.0 50 45 40 35 30 25 20 s l e w r a t e ( v / s ) supply voltage (v) v out = 2v p-p r l = 150 ? positive slew rate negative slew rate 24681246812 4 10khz 100khz 1mhz 4.2mhz 10 100 frequency (hz) n o i s e f l o o r nv/ hz () isl59117
8 fn6278.0 september 21, 2006 application information the isl59117 is a single-supply rail-to-rail triple (one s-video channel and one composite channel) video amplifier with internal sync tip clamps, a typical -3db bandwidth of 9mhz and slew rate of about 40v/s. this part is ideally suited for applications requiring high composite and s-video performance with very low po wer consumption. as the performance characteristics and features illustrate, the isl59117 is optimized for portable video applications. internal sync clamp embedded video dacs typically use ground as their most negative supply. this places the sync tip voltage at a minimum of 0v. presenting a 0v input to most single supply amplifiers will saturate the output stage of the amplifier resulting in a clipped sync tip and degraded video image. the isl59117 features an internal sync clamp and offset function that level shifts the entire video signal to the optimum level before it reaches the amplifiers? input stage. these features also help avoid saturation of the output stage of the amplifier by setting the signal closer to the best voltage range. the simplified block diagram on the front page shows the basic operation of the isl591 17?s sync clamp. the y and cvbs inputs? ac-coupled video sync signal is pulled negative by a current source at the input. when the sync tip goes below the comparator thres hold, the compar ator output goes high, pulling up on the input through the diode, forcing current into the coupling capacitor until the voltage at the input is again 0v, and the comparator turns off. this forces the sync tip clamp to always be 0v, setting the offset for the entire video signal. the c channel is slaved to the y channel and clamped to a 500mv level. the sallen key low pass filter the sallen key is a classic low pass configuration. this provides a very stable low pass function, and in the case of the isl59117, a three-pole roll-off at 9mhz. the three-pole function is accomplished with an rc low pass network placed in series with and before the sallen key. the first pole is formed by an rc network, with poles two and three generated with a sallen key, creating a nice three-pole roll-off at 9mhz. output coupling the isl59117 can be ac or dc coupled to its output. when ac coupling, a 220f coupling capacitor is recommended to ensure that low frequencies are passed, preventing video ?tilt? or ?droop? across a line. the isl59117?s internal sync cl amp makes it possible to dc couple the output to a video lo ad, eliminating the need for any ac coupling capacitors, sa ving board space, cost, and eliminating any ?tilt? or offset shift in the output signal. the trade off is larger supply current draw, since the dc component of the signal is now dissipated in the load resistor. typical load current for ac coupled signals is 5ma compared to 10ma for dc coupling. output drive capability the isl59117 does not have internal short circuit protection circuitry. if the output is s horted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. maximum reliability is maintained if the output current never exceeds 40ma. this limit is set by the design of t he internal metal interconnect. note that for transient short circuits, the part is robust. short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. in video applications this would be a 75 ? resistor and will provide adequate short circuit protection to the device. care should still be taken not to stress the device with a short at the output. figure 21. package power dissipation vs ambient temperature figure 22. package power dissipation vs ambient temperature typical performance curves (continued) 1 0.9 0.8 0.6 0.4 0.1 0 0 255075100 150 ambient temperature (c) p o w e r d i s s i p a t i o n ( w ) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 0.7 0.3 0.5 462mw j a = 2 1 6 c / w w l c s p ( 3 x 3 b u m p ) 952mw j a = 1 0 5 c / w w l c s p ( 3 x 3 b u m p ) 1.4 1.2 1 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) p o w e r d i s s i p a t i o n ( w ) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 isl59117
9 fn6278.0 september 21, 2006 power dissipation with the high output drive capab ility of the isl59117, it is possible to exceed the +125c absolute maximum junction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. the maximum power dissipation allowed in a package is determined according to: where: t jmax = maximum junction temperature t amax = maximum ambi ent temperature ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing: for sinking: where: v s = supply voltage i smax = maximum quiescent supply current v out = maximum output voltage of the application r load = load resistance tied to ground i load = load current power supply bypassing printed circuit board layout as with any modern operational amplifier, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as short as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, a single 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor from v s + to gnd will suffice. printed circuit board layout for good ac performance, parasitic capacitance should be kept to minimum. use of wire wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performance. pd max t jmax t amax ? ja -------------------------------------------- - = pd max v s i smax v s v out ? () + v out r l --------------- - = pd max v s i smax v out v s ? () + i load = isl59117
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6278.0 september 21, 2006 isl59117 wafer level chip scale package (wlcsp) pin a1 id area a e1 bottom view a b 12 c 3 b d 1 side view a 1 b a 2 top view bb d e sd w3x3.9a 3x3 array 9 ball wafer level chip scale package (for isl59116, isl59117 only) symbol millimeters notes a 0.62 +0.05 -0.08 - a 1 0.24 0.025 - a 2 0.38 ref. - b 0.32 0.03 - bb 0.30 ref. - d 1.45 0.05 - d 1 1.00 basic - e 1.45 0.05 - e 1 1.00 basic - e 0.50 basic - sd 0.00 basic - n93 rev. 1 6/06 notes: 1. dimensions are in millimeters. 2. dimensioning and tolerancing conform to asme 14.5m-1994. 3. symbol ?n? is the actual number of solder balls. 4. reference jedec mo-211-c, variation dd.
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